Keynote Speech I: Temporal Networks and Temporal Graphs
Paul G. Spirakis
Professor, Patras Univeristy (Greece) and U. Liverpool (UK)
President of the European Association for Theoretical Computer Science (EATCS).
Fellow of EATCS.
Member of Academia Europaea.
Abstract
We discuss here recent research by the speaker and others about Networks that change with time and about a nice abstraction for them (Temporal Graphs). This abstraction may model modern communication networks , social nets , transportation networks and even systems of interacting particles in Physics. We discuss causal paths , issues of temporal connectivity , temporal design , temporal exploration and we also propose some further research directions.
Short Bio of Prof. Spirakis
Paul G. Spirakis was born in 1955. He got his undergraduate Electrical Eng. Diploma from NTUA Greece and his MSc and PhD form Harvard University USA.
He has been a post-doc at Harvard , then a faculty at NYU - Courant Institute and then a Professor in the Dept. of Computer Eng. and Informatics of Patras University in Greece.
He has been the Director of the major Greek Institute CTI from 1996 till Sept. 2016.
He is now a Professor of Computer Science in Patras and Liverpool.
Paul is working on Algorithms and Complexity. He has done work in the fields of Distributed and Parallel Computing , in Random Graphs , network algorithms and recently in Algorithmic Game Theory.
Paul is a Fellow of EATCS , a Member of Academia Europaea and a Member of the ACM Council Europe. Paul is now the President of EATCS and also the Editor in Chief in the Journal Theoretical Computer Science (TCS) in track A. Paul has published significantly in Algorithms and Complexity.
Paul has served in many national and European high level bodies including being the Chair of the ERC Panel in Informatics for 2015-16.
Keynote Speech II: Coping with delay defects in deep submicron digital integrated circuits
Spyros Tragoudas, PhD
Professor and Chair
Director, NSF I/UCRC for Embedded Systems, SIUC site
Electrical and Computer Engineering Department
Southern Illinois University Carbondale
Abstract
Testing for delay defects is increasingly challenging in digital integrated circuits. Complex fault models must be used for the generation of input stimuli. Scalable automatic test pattern generation methods are presented, and approaches that identify the location of embedded delay defects are outlined.
Short Bio of Prof. Tragoudas
Spyros Tragoudas (BSc 1986, MSc 1988, PhD 1991) is a Professor and Department Chair at the Electrical and Computer Engineering (ECE) Department, Southern Illinois University at Carbondale (SIUC), and the Director of the National Science Foundation (NSF) Industry University Cooperative Research Center (IUCRC) on Embedded Systems at the SIUC site. He has held prior appointments with the faculty of the ECE Department at the University of Arizona, and with the faculty of the Computer Science Dept. at SIUC.
His current research interests are in the areas of VLSI Design and Test Automation and embedded systems. Dr. Tragoudas has published over eighty papers in journals and over hundred and fifty papers is peer-reviewed conference proceedings in these areas, and has received four outstanding paper awards for research in VLSI Testing. His research has been funded from federal agencies and industry. He has served and current serving on the editorial board of several journals, the technical program committees of many conferences, was the program chair of the DFTS’09, and the general chair of DFTS’10 and DFTS’17.
